Robust level converter design for sub-threshold logic

被引：12

作者：

Chang, Ik Joon ^{[1
]}

Kim, Jae-Joon ^{[1
]}

Roy, Kaushik ^{[1
]}

机构：

[1] Purdue Univ, Sch ECE, W Lafayette, IN 47906 USA

来源：

ISLPED '06: PROCEEDINGS OF THE 2006 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2006年

关键词：

sub-threshold logic; level converter; low power circuit design;

D O I：

10.1109/LPE.2006.4271800

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The large supply voltage difference between sub-threshlold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, Clock Synchronizer and Reduced Swing Inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500Khz between 20 degrees C and 40 degrees C with a supply voltage of 0.25V.

引用

页码：14 / 19

页数：6

共 10 条

[1]

CHEN C, 2002, IEEE T CIRCUITS SYST, V49

[2] Level conversion for dual-supply systems [J].