Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

被引：17

作者：

Brouzet, V. ^{[1
,2
,3
]}

Salem, B. ^{[1
,2
]}

Periwal, P. ^{[1
,2
]}

Rosaz, G. ^{[1
,2
]}

Baron, T. ^{[1
,2
]}

Bassani, F. ^{[1
,2
]}

Gentile, P. ^{[4
,5
]}

Ghibaudo, G. ^{[3
]}

机构：

[1] Univ Grenoble Alpes, LTM, F-38000 Grenoble, France

[2] CNRS, LTM, F-38000 Grenoble, France

[3] Univ Grenoble Alpes, MINATEC INPG, IMEP LAHC, F-38016 Grenoble, France

[4] Univ Grenoble Alpes, INAC SiNaPS SP2M, F-38000 Grenoble, France

[5] CEA, INAC SiNaPS SP2M, F-38000 Grenoble, France

来源：

APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING | 2015年 / 121卷 / 03期

关键词：

FIELD-EFFECT TRANSISTORS; ELECTRICAL CHARACTERISTICS; IMPACT;

D O I：

10.1007/s00339-015-9507-3

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper, we present the fabrication and electrical characterization of a MOS gated diode based on axially doped silicon nanowire (NW) p-i-n junctions. These nanowires are grown by chemical vapour deposition (CVD) using the vapour-liquid-solid (VLS) mechanism. NWs have a length of about with of doped regions (p-type and n-type) and of intrinsic region. The gate stack is composed of 15 nm of hafnium dioxide (), 80 nm of nickel and 120 nm of aluminium. At room temperature, , and an ratio of about with a very low current has been obtained. Electrical measurements are carried out between 90 and 390 K, and we show that the I (on) current is less temperature dependent below 250 K. We also observe that the ON current is increasing between 250 and 390 K. These transfer characteristics at low and high temperature confirm the tunnelling transport mechanisms in our devices.

引用

页码：1285 / 1290

页数：6

共 26 条

[1] Spatially Resolved Correlation of Active and Total Doping Concentrations in VLS Grown Nanowires [J].

Amit, Iddo ;

Givan, Uri ;

Connell, Justin G. ;

Paul, Dennis F. ;

Hammond, John S. ;

Lauhon, Lincoln J. ;

Rosenwaks, Yossi .

NANO LETTERS, 2013, 13 (06) :2598-2604

[2]

[Anonymous], ELECT DEV LETT

[3]

APPENZELLER J, 2008, ELECT DEV IEEE T, V55, P2827, DOI DOI 10.1109/TED.2008.2008011

[4] Dopant profiling in silicon nanowires measured by scanning capacitance microscopy [J].

Bassani, Franck ;

Periwal, Priyanka ;

Salem, Bassem ;

Chevalier, Nicolas ;

Mariolle, Denis ;

Audoit, Guillaume ;

Gentile, Pascal ;

Baron, Thierry .

PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS, 2014, 8 (04) :312-316

[5] P-channel tunnel field-effect transistors down to sub-50 nm channel lengths [J].

Bhuwalka, KK ;

Born, M ;

Schindler, M ;

Schmidt, M ;

Sulima, T ;

Eisele, I .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B) :3106-3109

[6] Silicon nanowire tunneling field-effect transistors [J].

Bjoerk, M. T. ;

Knoch, J. ;

Schmid, H. ;

Riel, H. ;

Riess, W. .

APPLIED PHYSICS LETTERS, 2008, 92 (19)

[7] Improved subthreshold characteristics in tunnel field-effect transistors using shallow junction technologies [J].

Chang, Hsu-Yu ;

Chopra, Saurabh ;

Adams, Bruce ;

Li, Jiping ;

Sharma, Shashank ;

Kim, Yihwan ;

Moffatt, Steve ;

Woo, Jason C. S. .

SOLID-STATE ELECTRONICS, 2013, 80 :59-62

[8] Practical Strategies for Power-Efficient Computing Technologies [J].

Chang, Leland ;

Frank, David J. ;

Montoye, Robert K. ;

Koester, Steven J. ;

Ji, Brian L. ;

Coteus, Paul W. ;

Dennard, Robert H. ;

Haensch, Wilfried .

PROCEEDINGS OF THE IEEE, 2010, 98 (02) :215-236

[9] Analytical temperature dependent model for nanoscale double-gate MOSFETs reproducing advanced transport models [J].

Cheralathan, Muthupandian ;

Sampedro, Carlos ;

Gamiz, Francisco ;

Iniguez, Benjamin .

SOLID-STATE ELECTRONICS, 2014, 98 :2-6

[10] Temperature impact on the tunnel fet off-state current components [J].

Der Agopian, Paula Ghedini ;

Martino, Marcio Dalla Valle ;

dos Santos Filho, Sebastiao Gomes ;

Martino, Joao Antonio ;

Rooyackers, Rita ;

Leonelli, Daniele ;

Claeys, Cor .

SOLID-STATE ELECTRONICS, 2012, 78 :141-146

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