Design and field programmable gate array implementation of cascade neural network based flux estimator for speed estimation in induction motor drives

This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives. The main focus of this study is the FPGA implementation of cascade NN based flux estimator. The major issues in FPGA implementation are optimisation of cost (resource) and execution time. A simple non-linear activation function called as Elliott function is used to reduce the execution time. To reduce the cost, and effectively utilise resource, the concept of layer multiplexing is adopted. The lowest bit precision needed for good performance of the estimator is identified and implemented. The proposed NN based flux estimator using simple excitation function and minimum bit precision is implemented using layer multiplexing technique. The designed estimator is tested on Spartan FPGA kit (3sd1800afg676-4) and the results obtained are presented.