Leakage and process variation effects in current testing on future CMOS circuits

被引：19
作者：
Keshavarzi, A
Tschanz, JW
Narendra, S
De, V
Roy, K
Hawkins, CF
Daasch, WR
Sachdev, M
机构：
[1] Intel Corp, Microproc Res Labs, Portland, OR USA
[2] Intel Labs, Hillsboro, OR USA
[3] Purdue Univ, W Lafayette, IN 47907 USA
[4] Univ New Mexico, Dept Elect & Comp Engn, Albuquerque, NM 87131 USA
[5] Portland State Univ, Integrated Circuits Design & Test Lab, Portland, OR 97207 USA
[6] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2002年 / 19卷 / 05期
关键词：
D O I：
10.1109/MDT.2002.1033790
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multiparameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.
引用
收藏
页码：36 / 43
页数：8
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