Fabrication of nanostructures on silicon surfaces on wafer scale by controlling self-organization processes

We describe a novel route for future Si integration technology in which atomically controlled nanostructures are designed to the level of full wafers based on self-organization processes. As an example of the scenario, we present a Ge quantum dot network where individual dots interact with the neighboring dots through tunneling barriers, Schottky junctions, and so on. Ge dots are patterned on Si(lll) surfaces by preferential nucleation of Ge islands at atomic steps and boundaries between reconstructed domains. It is then demonstrated that atomic step arrangement can be designed by patterning assisted control; this means that Ge quantum dot network can also be designed. Selective oxidation and silicidation in the Si/Ge systems are effectively utilized to form semiconductor/insulator/metal nanostructures from well-ordered semiconductor structures. Based on the above processes, we propose a new approach to design nanostructure integration organized on wafer scale. (C) 1996 American Vacuum Society.