Ultra-low power source coupled FET logic gate configuration in GaAs MESFET technology

被引：0

作者：

Bushehri, E ^{[1
]}

Bratov, V ^{[1
]}

Starosselski, V ^{[1
]}

Schlichter, T ^{[1
]}

Milenkovic, S ^{[1
]}

Timochenkov, V ^{[1
]}

机构：

[1] Middlesex Univ, Ctr Microelect, London N11 2NQ, England

来源：

ELECTRONICS LETTERS | 2000年 / 36卷 / 01期

关键词：

D O I：

10.1049/el:20000016

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A source coupled FET logic gate configuration is proposed for achieving high speed and low power dissipation. A frequency of 2.4GHz has been achieved based an measurements on a divide-by -20 frequency divider, dissipating only 12mW from a single 2V power supply. The performance of the gate in terms of speed is comparable to that of the previously reported high speed source coupled FET logic while dissipating a fraction of the power.

引用

页码：36 / 38

页数：3

共 50 条

[21] Ultra-low power digital subthreshold logic circuits
Soeleman, Hendrawan
Roy, Kaushik
Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 1999, : 94 - 96
[22] SPEED-POWER PROPERTY OF GAAS SCHOTTKY-BARRIER COUPLED SCHOTTKY-BARRIER GATE FET LOGIC
TOMIZAWA, K
HASHIZUME, N
MATSUMOTO, K
SUZUKI, F
ELECTRONICS LETTERS, 1981, 17 (21) : 821 - 822
[23] Tunnel-FET Inverters for Ultra-low Power Logic with Supply Voltage down to VDD=0.2 V
Richter, S.
Trellenkamp, S.
Schaefer, A.
Hartmann, J. M.
Bourdelle, K. K.
Zhao, Q. T.
Mantl, S.
2014 15TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS), 2014, : 13 - 16
[24] High-Performance Ultra-Low Power Junctionless Nanowire FET on SOI Substrate in Subthreshold Logic Application
Chen, Chun-Yu
Lin, Jyi-Tsong
Chiang, Meng-Hsueh
Kim, Keunwoo
2010 IEEE INTERNATIONAL SOI CONFERENCE, 2010,
[25] Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications
Yang, Libo
Zhu, Jiadi
Chen, Cheng
Wang, Zhixuan
Liu, Zexue
Huang, Qianqian
Ye, Le
Huang, Ru
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[26] GaAs source-coupled differential FET logic IC's electrical characteristics and logic abilities
Pripistsov, S.S.
Shagurin, I.I.
Atomnaya Energiya, 1992, (9-10): : 11 - 19
[27] SCHOTTKY-BARRIER COUPLED SCHOTTKY-BARRIER GATE GAAS-FET LOGIC
HASHIZUME, N
YAMADA, H
TOMIZAWA, K
ELECTRONICS LETTERS, 1981, 17 (01) : 51 - 52
[28] SCHOTTKY-BARRIER COUPLED SCHOTTKY-BARRIER GATE GAAS-FET LOGIC
HASHIZUME, N
YAMADA, H
KOJIMA, T
MATSUMOTO, K
INSTITUTE OF PHYSICS CONFERENCE SERIES, 1982, (63): : 557 - 562
[29] Subthreshold source-coupled logic circuits for ultra-low-power applications
Tajalli, Armin
Brauer, Elizabeth J.
Leblebici, Yusuf
Vittoz, Eric
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (07) : 1699 - 1710
[30] Dynamic Threshold Source Coupled Logic with Pushpull topology for Ultra Low Power Applications
Arora, Rajat
Khurana, Prateek
2ND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) 2015, 2015, : 968 - 972

← 1 2 3 4 5 →