A Time-Predictable Dual-Core prototype on FPGA

This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA.