A parallelized way to provide data encryption and integrity checking on a processor-memory bus

被引：17

作者：

Elbaz, Reouven ^{[1
,2
]}

Torres, Lionel ^{[1
]}

Sassatelli, Gilles ^{[1
]}

Guillemin, Pierre ^{[2
]}

Bardouillet, Michel ^{[2
]}

Martinez, Albert ^{[2
]}

机构：

[1] Univ Montpellier 2, CNRS, UMR C5506, LIRMM, Montpellier, France

[2] STMicroeiectron, Adv Syst Technol, Rousset, France

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

security; performance; design; algorithms; verification; data confidentiality and integrity; architectures; bus encryption;

D O I：

10.1109/DAC.2006.229264

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged between a SoC (System on Chip) and its external memory. The PE-ICE approach is based on an existing block-encryption algorithm to which the integrity checking capability is added. Simulation results show that the performance overhead of PE-ICE remains low (below 4%) compared to block-encryption-only systems (which provide data confidentiality only).

引用

页码：506 / +

页数：2

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