A High-Speed ADC for a Multi-Band 5G V2X Wireless Receiver

被引：2

作者：

Navidi, Seyedeh Masoumeh ^{[1
]}

Al Maharmeh, Hamza ^{[1
]}

Parekh, Samad ^{[2
]}

Wehbi, Ali ^{[3
]}

Alhawari, Mohammad ^{[1
]}

Ismail, Mohammed ^{[1
]}

机构：

[1] Wayne State Univ, Wayne Ctr Integrated Circuits & Syst WINCAS, Detroit, MI 48202 USA

[2] Synopsys Inc, Mountain View, CA USA

[3] GlobalFoundries, Santa Clara, CA USA

来源：

2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22) | 2022年

关键词：

5G Communication Systems; Frequency Plan; Time-Interleaved ADC; V2X; Vehicle to Everything; Transceivers; 5G-V2X; SAR ADC; INTERLEAVED SAR ADC; ARCHITECTURE; CONVERTER;

D O I：

10.1109/ISCAS48785.2022.9937936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a radio architecture for 5G Vehicle to Everything (V2X) applications. A frequency planning suitable for the aforementioned radio architecture is proposed. A programmable Time-Interleaved (TI) Successive Approximation Register (SAR) Analog to Digital Converter (ADC) required for this radio architecture is presented. The effect of process and temperature (PT) variations on the performance of Monotonic SAR ADC is investigated. A calibration technique is proposed to account for PT variations in the Monotonic SAR ADC. Additionally, simulation results for TI SAR ADC designed in 22nm FDSOI which works at two different sampling frequencies for V2X applications are presented.

引用

页码：331 / 335

页数：5

共 30 条

[1]

3GPP, 2017, DOCUMENT RP 170837

[2] A single-chip CMOS transceiver for 802.11a/b/g wireless LANs [J].

Ahola, R ;

Aktas, A ;

Wilson, J ;

Rao, KR ;

Jonsson, F ;

Hyyryläinen, I ;

Brolin, A ;

Hakala, T ;

Friman, A ;

Mäkiniemi, T ;

Hanze, J ;

Sandén, M ;

Wallner, D ;

Guo, Y ;

Lagerstam, T ;

Noguer, L ;

Knuuttila, T ;

Olofsson, P ;

Ismail, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2250-2258

[3]

[Anonymous], 2018, 3GPP TSG RAN M 80

[4]

[Anonymous], 2007, C2C 200 MAN

[5]

[Anonymous], 2018, 3GPP REL 15 OV

[6]

Anwar W, 2019, IEEE VTS VEH TECHNOL, DOI [10.1109/vtcfall.2019.8891313, 10.1109/pimrc.2019.8904104]

[7] TIME INTERLEAVED CONVERTER ARRAYS [J].

BLACK, WC ;

HODGES, DA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) :1022-1029

[8]

CAMP Vehicle Safety Communications Consortium, 2005, Vehicle safety communications project: Task 3 final report: identify intelligent vehicle safety applications enabled by DSRC

[9] A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration [J].

Chang, Dong-Jin ;

Choi, Michael ;

Ryu, Seung-Tak .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (09) :2691-2700

[10] A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration [J].

El-Chammas, Manar ;

Murmann, Boris .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (04) :838-847

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