Configurable microprocessor array for DSP applications

被引：0

作者：

Maslennikow, O ^{[1
]}

Shevtshenko, J ^{[1
]}

Sergyienko, A ^{[1
]}

机构：

[1] Tech Univ Koszalin, PL-75411 Koszalin, Poland

来源：

PARALLEL PROCESSING AND APPLIED MATHEMATICS | 2004年 / 3019卷

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The configurable microprocessor array for DSP applications is proposed, in which each cell is the microprocessor with RISC architecture, represented as a soft IP-core. This IP-core is generated automatically by the special soft-core generator, which is based on the approach to optimization of a microprocessor architecture for its further implementation in FPGA devices. Soft-core generator analyzes the executing program of each microprocessor of the array and eliminates all unused units from the resulting VHDL-model of the microprocessor. Therefore, hardware volume of each cell of this array is minimized, and is adapted to the used instruction subset. The soft-core generator provides both high throughput and minimized hardware volume with speedups the design process. It was probed in design the microprocessor array for solving the linear equation system with Toeplitz matrices.

引用

页码：36 / 41

页数：6

共 8 条

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