Metal Gate/High-κ Dielectric Gate Stack Reliability; Or How I Learned to Live with Trappy Oxides

被引：4

作者：

Linder, Barry P. ^{[1
]}

Cartier, E. ^{[1
]}

Krishnan, S. ^{[1
]}

机构：

[1] IBM TJ Watson Res Ctr Address, Yorktown Hts, NY 10706 USA

来源：

SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 3 | 2013年 / 53卷 / 03期

关键词：

D O I：

10.1149/05303.0187ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Three mechanisms primarily limit gate oxide scaling: bias temperature instability in both NFETs (PBTI) and PFETs (NBTI), and gate dielectric breakdown in NFETs (nTDDB). Strategies for reducing each mechanism are identified, and the overall effect of each mechanism on future scaling is discussed. Specialized ring oscillator structures that aid in the understanding of the effect of both PBTI and NBTI on circuit operation are explored.

引用

页码：187 / 192

页数：6

共 9 条

[1]

Cartier E, 2011, 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)

[2] On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si0.45Ge0.55 pMOSFETs [J].

Franco, J. ;

Kaczer, B. ;

Toledano-Luque, M. ;

Roussel, Ph. J. ;

Hehenberger, P. ;

Grasser, T. ;

Mitard, J. ;

Eneman, G. ;

Witters, L. ;

Hoffmann, T. Y. ;

Groeseneken, G. .

MICROELECTRONIC ENGINEERING, 2011, 88 (07) :1388-1391

[3]

Kerber A., 2009, ELECT DEVICE LETT, V30, P1347

[4]

Kim J., 2011, 2011 IEEE REL PHYS S, P47

[5]

Krishnan S, 2011, 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)

[6]

Linder BP, 2011, INT INTEG REL WRKSP, P1, DOI 10.1109/IIRW.2011.6142575

[7] The Effect of Interface Thickness of High-k/Metal Gate Stacks on NFET Dielectric Reliability [J].

Linder, Barry P. ;

Cartier, Eduard ;

Krishnan, Siddarth ;

Stathis, James H. ;

Kerber, Andreas .

2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2, 2009, :510-+

[8]

Wang M., ELECT DEVICE L UNPUB

[9]

Wu E., 2012, 2012 EL DEV M IEDM, P653

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