A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip

被引:0
作者
Joseph, Jan Moritz [1 ]
Wrieden, Sven [2 ]
Blochwitz, Christopher [2 ]
Garcia-Oritz, Alberto [3 ]
Pionteck, Thilo [1 ]
机构
[1] Otto von Guericke Univ, Inst Informat & Kommunikat Tech, D-39106 Magdeburg, Germany
[2] Univ Lubeck, Inst Tech Informat, D-23562 Lubeck, Germany
[3] Univ Bremen, Inst Electrodynam & Microelect, D-28359 Bremen, Germany
来源
2016 11TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC) | 2016年
关键词
Asymmetric; 3D-Network-on-Chip; Simulation Environment; SystemC; Benchmarking; Design Space Exploration; ON-CHIP;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.
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页数:8
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