Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

被引：0

作者：

Aura, Shourin Rahman ^{[1
]}

Huq, S. M. Ishraqul ^{[1
]}

Biswas, Satyendra N. ^{[1
]}

机构：

[1] Ahsanullah Univ Sci & Technol, Dept Elect & Elect Engn, Dhaka, Bangladesh

来源：

INTERNATIONAL JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING SYSTEMS | 2022年 / 13卷 / 09期

关键词：

SRAM; CMOS; dual port; figure of merit;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

引用

页码：823 / 829

页数：7

共 20 条

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