A 14-b 32 MS/s pipelined ADC with fast convergence comprehensive background calibration

This paper presents the first aggressively calibrated 14-b 32 MS/s pipelined ADC. The design uses a comprehensive digital background calibration engine that compensates for linear and nonlinear errors as well as capacitor mismatch in multi-bit DAC. Background calibration techniques that estimate the errors by correlating the output of ADC with the calibration signal have a very slow convergence rate. This paper also presents a fully digital technique to speed up the convergence in the error estimation procedure. By digitally filtering the input signal during the error estimation, the convergence rate of the calibration has been improved significantly. Implemented in TSMC 0.25 mu m technology, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm(2) of active area. Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.