High-Speed Architectures for Parallel BCH Decoders

被引：0

作者：

Wei Liu ^{[1
]}

Zhao Lifeng ^{[2
]}

机构：

[1] Beihang Univ, Sch Transportat Sci & Engn, Beijing 100191, Peoples R China

[2] JiLin Univ, Sch Vehicle engn, Jilin, Peoples R China

来源：

FRONTIERS OF MANUFACTURING AND DESIGN SCIENCE IV, PTS 1-5 | 2014年 / 496-500卷

关键词：

BCH code; High-Speed; hardware; throughput; VLSI architecture;

D O I：

10.4028/www.scientific.net/AMM.496-500.2269

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Bose-Chaudhuri-Hocquenghen(BCH) error-correcting codes are now widely used in communication system and digital technology. The original iterative method is complex and time-consuming operations. An inversion less decoding method for binary BCH codes was proposed to simplify the Berlekamp-Massey algorithm, which can eliminate the bottleneck in long BCH decoder. For our considered parallel decoder architecture, the simplicity of this new method makes a simplified VLSI implementation possible.

引用

页码：2269 / +

页数：2