A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance

被引：116

作者：

Baruah, Ratul K. ^{[1
]}

Paily, Roy P. ^{[1
]}

机构：

[1] Indian Inst Technol Guwahati, Dept Elect & Elect Engn, VLSI Design Lab, Gauhati 781039, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2014年 / 61卷 / 01期

关键词：

Dual-material gate (DMG); high-k spacer; intrinsic gain; junctionless transistor (JLT); unity gains cutoff frequency; workfunction; FIELD-EFFECT TRANSISTORS; STACK SON MOSFET; IMPACT; MODEL; ARCHITECTURE;

D O I：

10.1109/TED.2013.2292852

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high-k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (G(m)), early voltage (V-EA), and intrinsic gain (G(m)R(O)) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high-k spacer enhances the fringing electric fields through the spacer.

引用

页码：123 / 128

页数：6

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