Generative Adversarial Network for Integrated Circuits Physical Assurance Using Scanning Electron Microscopy

Recent advancements in Artificial Intelligence (AI) and Computer Vision (CV) provide the researchers in Failure Analysis and Reliability (FAR) as well as Hardware Security (HS) with new opportunities to design novel systems to locate security failures or malicious modifications. Such developments in automation and verification modes are extremely helpful in particular for government agencies who must physically assure chips with billions of transistors within critical applications. AI based techniques such as deep learning can provide a high-performance detection and recognition of elements from Scanning Electron Microscopic (SEM) images acquired from Integrated Circuits (ICs) and understand unseen images if they are trained well. However, they require a large and diverse set of images for building their knowledge. Possessing a large number of manufactured designs as well as the high cost and execution time associated with the image acquisition process are the major bottlenecks for creating a sufficient dataset. Alternatively, conventional data augmentation techniques such as intensity change, noise injection, rotation, and translation are not always able to project the variations of images acquired by SEM with different acquisition parameters. Furthermore, augmentations like rotation, translation, and shear might generate unacceptable augmented cell structures. This paper proposes a unique approach to detect logic cells on SEM images and use the extracted samples to generate diversified synthetic logic cell images by a Generative Adversarial Network (GAN) to address insufficient data problems. We introduce an image quality assessment metric for the synthetic dataset in order to study the qualification of generated samples for recognition computations.