Design and Analysis of CMOS Single Photon Counting Avalanche Photodiodes Integrated with Active Quenching Circuits

The CMOS SPADs (Single Photon Avalanche Diodes) integrated with active quenching circuits were fabricated on same chip using AMIS 0.7 Am high voltage CMOS process without any process modifications. The SPADs have N+/P-substrate structure and their diameter of photo sensing area are 25 mu m, 50 mu m, 100 mu m, 400 mu m, and 800 mu m. The avalanche multiplication is Occurred at 10.7 V, and the photocurrent gain at 11 V reverse bias voltage is about 1000. In zero bias condition, the maximum quantum efficiency appears at 650 nm wavelength, and it corresponds to around 30 %. The active quenching circuit is composed of a comparator, three monostable, and two MOS switch. As a circuit simulation results, the comparator and the monostable generate similar to 22 nsec and similar to 1 nsec delayed output pulse, respectively. The dead time of the active quenching circuits integrated with SPADs is about 100 nsec as a measured result.