Development of hierarchical testability design methodologies for analog/mixed-signal integrated circuits

The inductive fault analysis (IFA) technique has been adopted in the previous study for the development of a defect-oriented testability design methodology for analog/mixed-signal integrated circuits. The design methodology defines a collection of fault types and develops a set of testability design rules which define the parameter bounds, generates the test vectors, and valuates the fault coverage. However, the IFA technique requires a tremendous amount of computational time and thus being limited for small circuits. To reduce the computational complexity for reasonably large analog circuits, this paper presents a hierarchical fault macromodeling. Based on the fault modeling for primitive cells in a cell library, a hierarchical fault macromodeling process is developed for establishing macro library to simplify the testability design process.