Novel ESD protection structure with embedded SCR LDMOS for smart power technology

被引:34
作者
Lee, JH [1 ]
Shih, JR [1 ]
Tang, CS [1 ]
Liu, KC [1 ]
Wu, YH [1 ]
Shiue, RY [1 ]
Ong, TC [1 ]
Peng, YK [1 ]
Yue, JT [1 ]
机构
[1] Taiwan Semicond Mfg Co, Hsinchu, Taiwan
来源
40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2002年
关键词
Current distribution; Current measurement; Electrostatic discharge; Performance evaluation; Power transistors; Protection; Pulse measurements; Stress; Thyristors; Voltage;
D O I
10.1109/RELPHY.2002.996629
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a new robust ESD protection structure has been proposed for smart power technology. By inserting a P+ diffusion into the drain region of 40V-LDMOS power transistor, the embedded SCR (ESCR-LDMOS) device can be built and without changing any DC I-V characteristics of a 40V-LDMOS power transistor. It is also found that the method with P+ strap inserted into drain region (N+ in NW) can improve the ESD failure threshold from 1kV to 6kV for HBM and from 100V to 350V for MM.
引用
收藏
页码:156 / 161
页数:6
相关论文
共 5 条
[1]  
Duvvury C, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P345, DOI 10.1109/IEDM.1995.499211
[2]   Lateral DMOS design for ESD robustness [J].
Duvvury, C ;
Carvajal, F ;
Jones, C ;
Briggs, D .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :375-378
[3]  
DUVVURY C, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P407, DOI 10.1109/IEDM.1994.383381
[4]  
Jian-Hsing Lee, 1999, Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394), P162, DOI 10.1109/IPFA.1999.791327
[5]  
KUNZ K, 2001, EOS ESD S P, P13