A 10b 25MS/s 4.8mW 0.13um CMOS ADC for digital multimedia broadcasting applications

被引：3

作者：

Cho, Young-Jae ^{[1
]}

Sa, Doo-Hwan ^{[1
]}

Kim, Yong-Woo ^{[1
]}

Lee, Kyung-Hoon ^{[1
]}

Choi, Hee-Cheol ^{[1
]}

Lee, Seung-Hoon ^{[1
]}

Jeon, Young-Deuk ^{[2
]}

Lee, Seung-Chul ^{[2
]}

Kwon, Jong-Kee ^{[2
]}

机构：

[1] Sogang Univ, Dept Elect Engn, 1 Sinsoo Dong, Seoul 121742, South Korea

[2] Elect & Telecommun Res Inst, Sensor Signal Proc Team, Daejeon 305600, South Korea

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320892

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10b two-stage pipeline ADC implemented in a 0.13um CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm(2) and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply.

引用

页码：497 / 500

页数：4

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