Cross-coupling in 65nm Fully Integrated EDGE System On Chip Design and Cross-coupling prevention of complex 65nm SoC

被引：0

作者：

Bonnaud, Pierre-Henri ^{[1
]}

Sommer, Grit ^{[2
]}

机构：

[1] Infineon Technol, Mobile Phone Platform, Sophia Antipolis, France

[2] Infineon Technol AG, Package Layout, D-85579 Neubiberg, Germany

来源：

DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 | 2009年

关键词：

eWLB; Chip&Package Co-Design; SoC integration; cross-coupling; aggressors; victims;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Entry mobile phone market is a mass volume segment where the modem and application technologies are commoditized and fully proven. Nevertheless the cost and power reduction target continues to heavily drive leading edge innovations. Semiconductor companies strive to integrate more and more Printed Circuit Board (PCB) components into one single chip, without discontinuing the technology node shrink roadmap, from 130nm down to 65mn. This duality between integration level and aggressive silicon feature size reduction generates an innovative environment where design engineers must create new methodologies to cope with complex cross coupling mechanisms and additional power dissipation. This paper describes one aspect of the design methodology to reduce the die and package cross-talks, and focus on the package co-design flow. The chip being considered is a 65mn single chip System on Chip (SoC) including EDGE RF, Power Management Unit (PMU), Audio Front End (AFE) and FM Radio (FMR) circuits.

引用

页码：1045 / +

页数：2