An all-digital low ripples capacitive DC-DC converter with load tracking controller

被引：4

作者：

Bahry, Mohamed Khairy ^{[1
]}

El-Nozahi, Mohamed ^{[1
]}

Hegazi, Emad ^{[1
]}

机构：

[1] Ain Shams Univ, Fac Engn, Cairo, Egypt

来源：

INTEGRATION-THE VLSI JOURNAL | 2018年 / 62卷

关键词：

CMOS DC-DC converter; Fully integrated converter; Switched capacitor; NM CMOS;

D O I：

10.1016/j.vlsi.2018.02.007

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An all-digital Switched Capacitor (SC) DC-DC converter with a Switch Logic Controller and Optimizer (SLCO) is proposed in this paper. The SLCO achieves the maximum efficiency while keeping the output voltage ripples and load regulation at minimum values. Capacitance Modulation (CpM) and Pulse Frequency Modulation (PFM) are used to cover a wide dynamic range of load currents. Theoretical analysis and optimization algorithm are also presented to achieve the maximum efficiency. The SC converter is implemented in 0.13 pm CMOS technology using thick oxide I/O devices and achieves a maximum efficiency of 63% at power density of 0.095 W/mm(2). The SC converter delivers up to 100 mA load current for an output voltage of 1 V from a 3.6 V nominal input voltage. Output voltage ripples and load regulation are less than 16 mV and 0.02%/mA, respectively.

引用

页码：123 / 131

页数：9

共 9 条

[1] Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique [J].