IF: An intermediate representation and validation environment for timed asynchronous systems

被引:0
|
作者
Bozga, M
Fernandez, JC
Ghirvu, L
Graf, S
Krimm, JP
Mounier, L
机构
[1] VERIMAG, Ctr Equat, F-38610 Gieres, France
[2] IMAG, LSR, F-38402 St Martin Dheres, France
来源
FM'99-FORMAL METHODS | 1999年 / 1708卷
关键词
asynchrony; timed systems; timed automata; model-checking; static analysis;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Formal Description Techniques (FDT), such as LOTOS or SDL are at the base of a technology for the specification and the validation of telecommunication systems. Due to the availability of commercial tools, these formalisms are now being widely used in the industrial community. Alternatively, a number of quite efficient verification tools have been developed by the research community. But, most of these tools are based on simple ad hoc formalisms and the gap between them and real FDT restricts their use at industrial scale. This context motivated the development of an intermediate representation called IF which is presented in the paper. IF has a simple syntactic structure, but allows to express in a convenient way most useful concepts needed for the specification of timed asynchronous systems. The benefits of using IF are multiples. First, it is general enough to handle significant subsets of most FDTs, and in particular a translation from SDL to IF is already implemented. Being built upon a mathematically sound model (extended timed automata) it allows to properly evaluate different semantics for FDTs, in particular with respect to time considerations. Finally, IF can serve as a basis for interconnecting various tools into a unified validation framework. Several levels of IF program representations are already available via well defined APIs and allow to connect tools ranging from static analyzers to model-checkers.
引用
收藏
页码:307 / 327
页数:21
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