A variable gain high linearity low power baseband filter for WLAN

被引：0

作者：

Ranganathan, S ^{[1
]}

Fiez, T ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75265 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 4(th) order low-pass baseband filter for WLAN applications, implemented in a 1.5 V 3 V 0.15 mum CMOS process. The active-RC configuration uses single amplifier biquads (SABs) to save power and has resistor and capacitor arrays to provide variable gain and bandwidth trimming. The biquads are implemented using three-stage opamps and a hybrid pi-to-Tee transformation network for the resistor arrays, so that higher linearity than conventional Sallen-Key circuits may be obtained. The filter achieves a measured THD of -72 dB at 1 MHz.

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页码：845 / 848

页数：4

相关论文

共 13 条

[1] HIGH-LINEARITY CONTINUOUS-TIME FILTER IN 5-V VLSI CMOS [J].

DURHAM, AM ;

REDMANWHITE, W ;

HUGHES, JB .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (09) :1270-1276

[2] INTEGRATED CONTINUOUS-TIME BALANCED FILTERS FOR 16-B DSP INTERFACES [J].

DURHAM, AM ;

REDMANWHITE, W .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (07) :835-839

[3]

EASWARAN P, 2003, Patent No. 6642779

[4] A low distortion linear-tunable continuous time 488 kHz fifth order Bessel filter [J].

Egerer, J ;

Desel, T ;

Popken ;

Boxho, J ;

Macq, D ;

Cornil, JP .

ELEVENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE - PROCEEDINGS, 1998, :47-50

[5] Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS [J].

Gopinathan, V ;

Tarsia, M ;

Choi, D .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (12) :1698-1707

[6] Design of low-voltage CMOS continuous-time filter with on-chip automatic tuning [J].

Huang, HZ ;

Lee, EKF .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (08) :1168-1177

[7] A multistage amplifier technique with embedded frequency compensation [J].

Ng, HT ;

Ziazadeh, RM ;

Allstot, DJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (03) :339-347

[8] AN OPTIMIZED COMPENSATION STRATEGY FOR 2-STAGE CMOS OP AMPS [J].

PALMISANO, G ;

PALUMBO, G .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1995, 42 (03) :178-182

[9] Design methodology and advances in nested-miller compensation [J].

Palumbo, G ;

Pennisi, S .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2002, 49 (07) :893-903

[10]

PYYKONEN JK, 2001, P IEEE INT CIRC SYST, V1, P244