An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes

被引：175

作者：

Casper, BK ^{[1
]}

Haycock, M ^{[1
]}

Mooney, R ^{[1
]}

机构：

[1] Intel Labs, Circuit Res, Hillsboro, OR USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015043

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces an accurate method of modeling the performance of high-speed chip-to-chip signaling systems. Implemented in a simulation tool, it precisely accounts for intersymbol interference, cross-talk and echos as well as circuit related effects such as thermal noise, power supply noise and receiver jitter. We correlated the simulation tool to actual measurements of a high-speed signaling system and then used this tool to make tradeoffs between different methods of chip-to-chip signaling with and without equalization.

引用

页码：54 / 57

页数：4

共 7 条

[1]

HAYCOCK M, 1997, HOT INT 5 S REC AUG, P149

[2]

HAYCOCK M, 2001, ISSCC 2001 DIGEST TE

[3] CALCULATING ERROR PROBABILITIES FOR INTERSYMBOL AND COCHANNEL INTERFERENCE [J].