Optimization of a dc to dc Boost Converter using Interleaved Command Technique

In this paper is optimized by numerical simulations a dc to dc boost converter with two parallel stages using the interleaved command technique. A comparative study between three converter topologies - one stage, two parallel stages and two interleaved stages is presented. First, the interleaved command converter is modeled in MULTISIM and is tested under many output loads. For comparison, simulations with constant and controlled duty cycle of the PWM are performed. The main characteristics of the three topologies are discussed: input current, input current ripple, output voltage ripple, and the MOSFET peak current.