Metal gate technology for 45nm and beyond

被引：0
|
作者：
Shibahara, Kentaro [1 ]
机构：
[1] Hiroshima Univ, Res Ctr Nanodevices & Syst, Higashihiroshima 7398527, Japan
来源：
2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Metal gate is one of the most expected technologies for CMOS device performance improvement. However, its integration to CMOS devices is not so easy compared with poly-Si gate devices. hi addition it needs a workfunction tuning method to adjust FET threshold voltage. In the presentation, these problems will be discussed based on author's research result of Mo and FUSI (Fully Silicided) gate referring state of the art of this field.
引用
收藏
页码：105 / 106
页数：2
相关论文
共 50 条
  • [1] Advanced CMOS technology beyond 45nm node
    Kawanaka, Shigeru
    Hokazono, Akira
    Yasutake, Nobuaki
    Tatsumura, Kosuke
    Koyama, Masato
    Toyoshima, Yoshiaki
    2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 164 - +
  • [2] Technology modeling and characterization beyond the 45nm node
    Nassif, Sani R.
    2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 132 - 132
  • [3] Litho metrology challenges for the 45nm technology node and beyond
    Allgair, John A.
    Bunday, Benjamin D.
    Bishop, Mike
    Lipscomb, Pete
    Orji, Ndubuisi G.
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XX, PTS 1 AND 2, 2006, 6152
  • [4] Double-Gate CMOS evaluation for 45nm technology node
    Chiang, MH
    An, JX
    Krivokapic, Z
    Yu, B
    NANOTECH 2003, VOL 2, 2003, : 326 - 329
  • [5] MOSFET modeling for 45nm and beyond
    Cao, Yu
    McAndrew, Colin
    IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 638 - +
  • [6] SPECTRE Modeling for 45nm and Beyond
    Yin Chang-yong
    Hao Bo
    ICCEE 2008: PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON COMPUTER AND ELECTRICAL ENGINEERING, 2008, : 799 - 801
  • [7] Reliability challenges for 45nm and beyond
    McPherson, J. W.
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 176 - 181
  • [8] Application challenges with double patterning technology (DPT) beyond 45nm
    Park, Jungchul
    Hsu, Stephen
    Van Den Broeke, Douglas
    Chen, J. Fung
    Dusa, Mircea
    Socha, Robert
    Finders, Jo
    Vleeming, Bert
    van Oosten, Anton
    Nikolsky, Peter
    Wiaux, Vincent
    Hendrickx, Eric
    Bekaert, Joost
    Vandenberghe, Geert
    PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2, 2006, 6349
  • [9] Ion Implantation Technology and System for beyond 45nm node Devices
    Tanjyo, Masayasu
    Nagayama, Tsutomu
    Hamamoto, Nariaki
    Umisedo, Sei
    Koga, Yuji
    Maehara, Noriaki
    Une, Hideyasu
    Nogami, Takashi
    Hino, Masayoshi
    Kobayashi, Tomoaki
    Fujita, Hideki
    Matsumoto, Takao
    Yoshimura, Yosuke
    Sakai, Shigeki
    Nagai, Nobuo
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1284 - 1287
  • [10] The Impact of Stain Technology on FUSI Gate SOI CMOSFET and Device Performance Enhancement for 45nm node and Beyond
    Yeh, Wen-Kuan
    Wang, Jean-An
    Lin, Chien-Ting
    Cheng, Li-Wei
    Ma, Mike
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 130 - +
12345