Multithreaded architectural support for speculative trace scheduling in VLIW processors

被引：1

作者：

Agarwal, M ^{[1
]}

Nandy, SK ^{[1
]}

van Eijndhoven, J ^{[1
]}

Balakrishanan, S ^{[1
]}

机构：

[1] Indian Inst Sci, SERC, CADL, Bangalore 560012, Karnataka, India

来源：

15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/SBCCI.2002.1137635

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler's scheduler. We propose a multithreaded architectural support for speculative trace scheduling in VLIW processors. In this multithreaded architecture the next most probable trace is speculatively executed, overlapping the stall cycles of the processor during cache misses and page faults. Switching between traces is achieved with the help of special hardware units viz. Operation State Buffers and Trace Buffers. We observe an 8.39% reduction in the overall misprediction penalty as compared to that incurred when the stall cycles due to cache misses alone are not overlapped.

引用

页码：43 / 48

页数：6

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