A New Modular and Symmetric Full Adder/Subtractor in Quantum-Dot Cellular Automata Nanocomputing

被引:2
|
作者
Abdullah-Al-Shafi, Md [1 ]
Behar, Ali Newaz [2 ,3 ]
Wahid, Khan A. [2 ]
机构
[1] Univ Dhaka, IIT, Dhaka 1000, Bangladesh
[2] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK S7N 5A9, Canada
[3] Mawlana Bhashani Sci & Technol Univ, Dept Informat & Commun Technol, Tangail 1902, Bangladesh
基金
加拿大自然科学与工程研究理事会;
关键词
Quantum-Dot Cellular Automata; Nanotechnology; Full Adder-Subtractor (FAS); Energy Dissipation; QCAPro; ADDER-SUBTRACTOR; DESIGN; QCA; MULTIPLEXER; ARCHITECTURE; DISSIPATION; SIMULATION; CIRCUITS; GATE;
D O I
10.1166/jno.2019.2630
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Quantum-dot cellular automata (QCA) is incipient nanotechnology and potential substitute to orthodox CMOS archetypes at nano extent that assures to conceive digital circuits with minimal energy, extreme speed, and particularly dense structures. In this study, a new high-speed and low intricacy QCA full adder-subtractor (FAS) configuration is presented by utilizing the formulations of five inputs majority gate. The proposed circuit is authenticated using the QCADesigner 2.0.3, and based on the outcomes, it is perceived that the outlined FAS is a competent arithmetic logic circuit, and has minimal circuit intricacy, reduced latency and moderated extent compared to existing circuits. Furthermore, a comprehensive transmission route of the proposed FAS is also outlined. QCAPro, a popular energy estimation engine is applied to estimate the energy depletion of the proposed circuit. It is perceived that the designed FAS dissipates minimal energy than existing designs.
引用
收藏
页码:1275 / 1282
页数:8
相关论文
共 50 条
  • [41] DESIGN OF NOVEL EFFICIENT FULL ADDER CIRCUIT FOR QUANTUM-DOT CELLULAR AUTOMATA TECHNOLOGY
    Mokhtari, Dariush
    Rezai, Abdalhossein
    Rashidi, Hamid
    Rabiei, Faranak
    Emadi, Saeid
    Karimi, Asghar
    FACTA UNIVERSITATIS-SERIES ELECTRONICS AND ENERGETICS, 2018, 31 (02) : 279 - 285
  • [42] An Efficient Design of Adder/Subtractor Circuit using Quantum Dot Cellular Automata
    Bardhan, Rajon
    Sultana, Tania
    Lisa, Nusrat Jahan
    2015 18TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT), 2015, : 495 - 500
  • [43] Novel Efficient Adder Circuits for Quantum-Dot Cellular Automata
    Sayedsalehi, Samira
    Moaiyeri, Mohammad Hossein
    Navi, Keivan
    JOURNAL OF COMPUTATIONAL AND THEORETICAL NANOSCIENCE, 2011, 8 (09) : 1769 - 1775
  • [44] Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata
    Pudi, Vikramkumar
    Sridharan, K.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (09) : 1535 - 1548
  • [45] Design of a 1-Bit Half and Full Subtractor using a Quantum-Dot Cellular Automata (QCA)
    Ramachandran, S. S.
    Kumar, K. J. Jegadish
    2017 IEEE INTERNATIONAL CONFERENCE ON POWER, CONTROL, SIGNALS AND INSTRUMENTATION ENGINEERING (ICPCSI), 2017, : 2324 - 2327
  • [46] Implementing a one-bit reversible full adder using quantum-dot cellular automata
    Zahra Mohammadi
    Majid Mohammadi
    Quantum Information Processing, 2014, 13 : 2127 - 2147
  • [47] An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder
    Angizi, Shaahin
    Danehdaran, Fahimeh
    Sarmadi, Soheil
    Sheikhfaal, Shadi
    Bagherzadeh, Nader
    Navi, Keivan
    JOURNAL OF LOW POWER ELECTRONICS, 2015, 11 (02) : 173 - 180
  • [48] Implementing a one-bit reversible full adder using quantum-dot cellular automata
    Mohammadi, Zahra
    Mohammadi, Majid
    QUANTUM INFORMATION PROCESSING, 2014, 13 (09) : 2127 - 2147
  • [49] A novel controllable inverter and adder/subtractor in quantum-dot cellular automata using cell interaction based XOR gate
    Safoev, Nuriddin
    Jeon, Jun-Cheol
    MICROELECTRONIC ENGINEERING, 2020, 222
  • [50] Novel efficient fault-tolerant full-adder for quantum-dot cellular automata
    Farazkish, Razieh
    INTERNATIONAL JOURNAL OF NANO DIMENSION, 2018, 9 (01) : 58 - 67