A New Modular and Symmetric Full Adder/Subtractor in Quantum-Dot Cellular Automata Nanocomputing

被引:2
|
作者
Abdullah-Al-Shafi, Md [1 ]
Behar, Ali Newaz [2 ,3 ]
Wahid, Khan A. [2 ]
机构
[1] Univ Dhaka, IIT, Dhaka 1000, Bangladesh
[2] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK S7N 5A9, Canada
[3] Mawlana Bhashani Sci & Technol Univ, Dept Informat & Commun Technol, Tangail 1902, Bangladesh
基金
加拿大自然科学与工程研究理事会;
关键词
Quantum-Dot Cellular Automata; Nanotechnology; Full Adder-Subtractor (FAS); Energy Dissipation; QCAPro; ADDER-SUBTRACTOR; DESIGN; QCA; MULTIPLEXER; ARCHITECTURE; DISSIPATION; SIMULATION; CIRCUITS; GATE;
D O I
10.1166/jno.2019.2630
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Quantum-dot cellular automata (QCA) is incipient nanotechnology and potential substitute to orthodox CMOS archetypes at nano extent that assures to conceive digital circuits with minimal energy, extreme speed, and particularly dense structures. In this study, a new high-speed and low intricacy QCA full adder-subtractor (FAS) configuration is presented by utilizing the formulations of five inputs majority gate. The proposed circuit is authenticated using the QCADesigner 2.0.3, and based on the outcomes, it is perceived that the outlined FAS is a competent arithmetic logic circuit, and has minimal circuit intricacy, reduced latency and moderated extent compared to existing circuits. Furthermore, a comprehensive transmission route of the proposed FAS is also outlined. QCAPro, a popular energy estimation engine is applied to estimate the energy depletion of the proposed circuit. It is perceived that the designed FAS dissipates minimal energy than existing designs.
引用
收藏
页码:1275 / 1282
页数:8
相关论文
共 50 条
  • [31] Efficient Design of Decimal Full Adder Using Quantum-dot Cellular Automata
    Li, Zeqiang
    Chu, Zhufei
    Wang, Lunyao
    Xia, Yinshui
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1373 - 1375
  • [32] An optimized design of full adder based on nanoscale quantum-dot cellular automata
    Seyedi, Saeid
    Navimipour, Nima Jafari
    OPTIK, 2018, 158 : 243 - 256
  • [33] Nano-scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum-dot cellular automata
    Das, Jadav Chandra
    De, Debashis
    INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2023, 36 (05)
  • [34] Quantum-Dot Cellular Automata Serial Decimal Adder
    Gladshtein, Michael
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2011, 10 (06) : 1377 - 1382
  • [35] Adder designs and analyses for quantum-dot cellular automata
    Cho, Heumpil
    Swartzlander, Earl E., Jr.
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2007, 6 (03) : 374 - 383
  • [36] Adder and Multiplier Design in Quantum-Dot Cellular Automata
    Cho, Heumpil
    Swartzlander, Earl E., Jr.
    IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (06) : 721 - 727
  • [37] Novel efficient full adder and full subtractor designs in quantum cellular automata
    Mostafa Sadeghi
    Keivan Navi
    Mehdi Dolatshahi
    The Journal of Supercomputing, 2020, 76 : 2191 - 2205
  • [38] Novel efficient full adder and full subtractor designs in quantum cellular automata
    Sadeghi, Mostafa
    Navi, Keivan
    Dolatshahi, Mehdi
    JOURNAL OF SUPERCOMPUTING, 2020, 76 (03): : 2191 - 2205
  • [39] Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata
    Farazkish, Razieh
    Khodaparast, Fatemeh
    MICROPROCESSORS AND MICROSYSTEMS, 2015, 39 (06) : 426 - 433
  • [40] Design of n-bit Full Adder Based on Quantum-Dot Cellular Automata
    Zhang H.
    Xie G.-J.
    Zhang Y.-Q.
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2024, 52 (02): : 626 - 632