Effects of mode conversion on parasitic coupling in high-speed VLSI circuits

被引:1
|
作者
Quéré, Y [1 ]
Le Gouguec, T [1 ]
Martin, PM [1 ]
Le Berre, D [1 ]
Huret, F [1 ]
机构
[1] CNRS, Lab Electron & Syst Telecommun, UMR 6165, F-29285 Brest, France
关键词
D O I
10.1109/SPI.2004.1409050
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The mode conversion means that a modification of the Electromagnetic Field configuration occurs, generally, after discontinuities. In deep submicron digital ULSI circuits, the mode conversion analysis is indispensable to identify the signal return path, the return current distribution and, therefore, for an accurate inductance modelling which remains a challenging problem [1]. On the other hand, switching activity of high speed CMOS circuit may produce large current derivatives in wires (crosstalk) and substrate. These current transients can generate large potential surges and coupled noise. In this mind, a reduction of the mode conversion phenomenon decreases noise in high speed ULSI circuits [2] [3]. We have investigated the mode conversion., in the frequency domain, for multiple-line inter-layer transitions in CMOS devices. The signal integrity analysis in time domain proved the detrimental effects of mode conversion. Finally, we confirmed that our design rule reduces the mode conversion phenomenon in the case of transition with multiple coupled lines.
引用
收藏
页码:193 / 196
页数:4
相关论文
共 50 条
  • [31] Gate-level exception handling design for noise reduction in high-speed VLSI circuits
    Chang, Sanghoan
    Choi, Gwan
    20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 109 - +
  • [32] Modeling and Coupling Effects Analysis of a High-speed Aircraft
    Feng, Dongzhu
    Wang, Xin
    2008 IEEE/ASME INTERNATIONAL CONFERENCE ON ADVANCED INTELLIGENT MECHATRONICS, VOLS 1-3, 2008, : 1137 - +
  • [33] PROGRAM CALCULATES LOAD EFFECTS OF HIGH-SPEED DIGITAL CIRCUITS
    FLORA, LP
    ELECTRONICS, 1971, 44 (24): : 70 - &
  • [34] Addressing a high-speed D/A converter design for mixed-mode VLSI systems
    Baek, KH
    Choe, MJ
    Merlo, E
    Kang, SM
    2003 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, 2003, : 21 - 26
  • [35] Addressing a high-speed D/A converter design for mixed-mode VLSI systems
    Baek, KH
    IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (05): : 1053 - 1060
  • [36] HIGH-SPEED SIGNED DIGITAL MULTIPLIERS FOR VLSI
    LO, HY
    MICROPROCESSING AND MICROPROGRAMMING, 1990, 29 (04): : 205 - 215
  • [37] INTERCONNECTION DELAY IN VERY HIGH-SPEED VLSI
    ZHOU, D
    PREPARATA, FP
    KANG, SM
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1991, 38 (07): : 779 - 790
  • [38] Optimization of high-speed VLSI interconnects: A review
    Zhang, QJ
    Wang, F
    Nakhla, M
    INTERNATIONAL JOURNAL OF MICROWAVE AND MILLIMETER-WAVE COMPUTER-AIDED ENGINEERING, 1997, 7 (01): : 83 - 107
  • [39] HIGH-SPEED VLSI PACKAGING WITH A SYSTEM PERSPECTIVE
    DOYLE, GJ
    SHEEHAN, BJ
    PROCEEDINGS OF THE TECHNICAL CONFERENCE : NINTH ANNUAL INTERNATIONAL ELECTRONICS PACKAGING CONFERENCE, VOLS 1 AND 2, 1989, : 1190 - 1202
  • [40] VLSI ARCHITECTURES FOR HIGH-SPEED RANGE ESTIMATION
    SASTRY, R
    RANGANATHAN, N
    JAIN, RC
    IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, 1995, 17 (09) : 894 - 899