Yield and speed optimization of a latch-type voltage sense amplifier

被引：317
作者：
Wicht, B [1 ]
Nirschl, T
Schmitt-Landsiedel, D
机构：
[1] Texas Instruments Deutschland GmbH, Mixed Signal Power & Control, D-85350 Freising Weihenstephan, Germany
[2] Tech Univ Munich, D-80333 Munich, Germany
[3] Infineon Technol, D-81609 Munich, Germany
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 07期
关键词：
current sensing; latch delay; latch-type sense amplifier; sense amplifier; SRAM circuits; SRAM yield; yield optimization;
D O I：
10.1109/JSSC.2004.829399
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input dc level, transistor sizing, and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input dc bias voltage. A figure of merit indicates that an input dc level of 0.7 V-DD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
引用
收藏
页码：1148 / 1158
页数：11
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