Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio

被引:35
作者
Sayed, D [1 ]
Dessouky, M [1 ]
机构
[1] Ain Shams Univ, Fac Engn, Cairo 11517, Egypt
来源
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS | 2002年
关键词
D O I
10.1109/DATE.2002.998358
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling identical size unit capacitors in a common-centroid geometry. In this paper, a general algorithm for fitting arbitrary capacitor ratios in a common-centroid unit-capacitor array is presented The algorithm gives special care to both non-integer and identical ratios in order to minimize mismatch. A method for capacitance mismatch estimation based upon an oxide gradient model is also introduced It enables the comparison of different unit-capacitor array assignments. Layout issues are discussed with emphasis on a generic routing model. Both the algorithm and the mismatch estimation method are implemented in an automatic capacitor array generation tool.
引用
收藏
页码:576 / 580
页数:5
相关论文
共 11 条
[1]   Analog layout using ALAS! [J].
Bruce, JD ;
Li, HW ;
Dallabetta, MJ ;
Baker, RJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (02) :271-274
[2]   KOAN ANAGRAM-II - NEW TOOLS FOR DEVICE-LEVEL ANALOG PLACEMENT AND ROUTING [J].
COHN, JM ;
GARROD, DJ ;
RUTENBAR, RA ;
CARLEY, LR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (03) :330-342
[3]  
FELT E, 1994, P ACM, P272
[4]   A PERFORMANCE-DRIVEN PLACEMENT TOOL FOR ANALOG INTEGRATED-CIRCUITS [J].
LAMPAERT, K ;
GIELEN, G ;
SANSEN, WM .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (07) :773-780
[5]   Current mirror layout strategies for enhancing matching performance [J].
Lan, MF ;
Tammineedi, A ;
Geiger, R .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2001, 28 (01) :9-26
[6]   ALL-MOS CHARGE REDISTRIBUTION ANALOG-TO-DIGITAL CONVERSION TECHNIQUES .1. [J].
MCCREARY, JL ;
GRAY, PR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (06) :371-379
[7]   SYSTEMATIC CAPACITANCE MATCHING ERRORS AND CORRECTIVE LAYOUT PROCEDURES [J].
MCNUTT, MJ ;
LEMARQUIS, S ;
DUNKLEY, JL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (05) :611-616
[8]   MATCHING PROPERTIES OF MOS-TRANSISTORS [J].
PELGROM, MJM ;
DUINMAIJER, ACJ ;
WELBERS, APG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1433-1440
[9]   RANDOM ERROR EFFECTS IN MATCHED MOS CAPACITORS AND CURRENT SOURCES [J].
SHYU, JB ;
TEMES, GC ;
KRUMMENACHER, F .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (06) :948-955
[10]  
TAYLOR RCJ, 1995, ANALOG CIRCUIT DESIGN, P203