共 14 条
- [1] [Anonymous], CERNLHCC2013008
- [2] Simulation of digital pixel readout chip architectures with the RD53 System Verilog-UVM verification environment using Monte Carlo physics data [J]. JOURNAL OF INSTRUMENTATION, 2016, 11
- [3] Demaria N., 2015, P 6 IEEE INT WORKSH, P49
- [4] Demaria N., POS IFD2014
- [5] Garcia-Sciveres M., CERNRD53PUB15001
- [6] Karagounis Michael, 2009, Proceedings of the 35th European Solid-State Circuits Conference. ESSCIRC 2009, P276, DOI 10.1109/ESSCIRC.2009.5325974
- [7] 1-Grad total dose evaluation of 65nm CMOS technology for the HL-LHC upgrades [J]. JOURNAL OF INSTRUMENTATION, 2015, 10
- [8] Monteil E., 2016, P PIX 2016 INT WORKS
- [9] A Low-Power Low-Noise Synchronous Pixel Front-End Chain in 65 nm CMOS Technology with Local Fast ToT Encoding and Autozeroing for Extreme Rate and Radiation at HL-LHC [J]. 2015 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (NSS/MIC), 2015,
- [10] Ratti L., 2015, P IEEE NUCL SCI S ME, P1