Hardware Efficient Double Diamond Search Block Matching Algorithm for Fast Video Motion Estimation

被引:6
作者
Shah, Nehal N. [1 ]
Dalal, Upena D. [2 ]
机构
[1] Sarvajanik Coll Engn & Technol, Surat, India
[2] SV Natl Inst Technol, Surat, India
来源
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2016年 / 82卷 / 01期
关键词
Motion estimation (ME); Block matching algorithm (BMA); Hardware efficient double diamond search (HEDDS); Sum of absolute difference (SAD); Search iterations; PATTERNS;
D O I
10.1007/s11265-015-0993-5
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Application of video in multimedia communication has become feasible due to efficient block matching algorithm (BMA) based motion estimation (ME) and motion compensation (MC) methods, that facilitate high data compression. To sustain visual quality of video, large amount of computation is involved in ME which can be reduced by fast search BMA and making fast search faster by various means like predicting initial search center (ISC) and early search termination. But more challenging work is to design an architecture which performs computation hungry search process in fewer clock cycles which will actually make fast search rapid for real time encoding. Implementations are available for matching multiple macroblocks in single clock cycle, but bottleneck is accessing macroblocks from memory while following sequential irregular search patterns of most of fast search algorithms. This paper proposes a novel, Hardware Efficient Double Diamond Search (HEDDS) algorithm which reaches far in search window more rapidly to identify best match and minimizes number of iterations of search pattern and hence diminish required clock cycles to read macroblocks from memory. From implementation perspective, HEDDS is up to 7.5 % to 33 % faster than existing BMAs and also offers reasonably good quality of encoding. With variable block size, HEDDS demonstrate average BD-PSNR improvement of 0.381, 0.088, 0.87 and 0.233 dB at BD-bitrate drop of 12.994 %, 2.499 %, 25.599 %, 6.887 % in comparison of HS, HMDS, LDPS and UMHS correspondingly. Proposed HEDDS architecture can process 259 HD frames per second in average case for fixed block size which is promising figure for real time encoding on devices having inadequate computational resources.
引用
收藏
页码:115 / 135
页数:21
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