Optimisation of Reed-Muller PLA implementations

被引:16
作者
Wang, L [1 ]
Almaini, AEA [1 ]
机构
[1] Napier Univ, Sch Engn, Edinburgh EH10 5DT, Midlothian, Scotland
来源
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 2002年 / 149卷 / 02期
关键词
D O I
10.1049/ip-cds:20020354
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Decomposition techniques are utilised for mixed polarity Reed-Muller minimisation, which lead to Reed-Muller programmable logic array implementations for Boolean functions. The proposed algorithm produces a simplified mixed polarity Reed-Muller format from the conventional sum-of-products input based on a top-down strategy. The output format belongs to the most general class of AND/XOR forms, namely exclusive-OR sum-of-products. This method is further generalised to very large multiple output Boolean functions. The developed decomposition method is implemented in the C language and tested with MCNC and IWLS'93 benchmarks. Experimental results show that the decomposition method can produce much better results than Espresso for many test cases. This efficient method offers compact Reed-Muller programmable logic array implementations with the added advantage of easy testability, in contrast to the conventional programmable logic array realisations.
引用
收藏
页码:119 / 128
页数:10
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