Industrial experience with test generation languages for processor verification

被引：22

作者：

Behm, M ^{[1
]}

Ludden, J ^{[1
]}

Lichtenstein, Y ^{[1
]}

Rimon, M ^{[1
]}

Vinov, M ^{[1
]}

机构：

[1] IBM Dev Ctr, Austin, TX USA

来源：

41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004 | 2004年

关键词：

functional verification; processor verification; test generation;

D O I：

10.1145/996566.996578

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.

引用

页码：36 / 40

页数：5

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