A Compensation Technique for SAR ADC Comparator Noise

This paper proposes a new way to compensate comparator errors in successive approximation analog-to-digital convertor (SAR ADC). The method adds negatively biased capacitance to traditional binary-scaled compensation, increasing ADC accuracy by up to 20%. A novel digital-to-analog convertor (DAC) structure is introduced to further increase its efficiency, which reduces total capacitance by 80%. According to mathematical and Cadence simulation, the proposed method provides an efficient trade-off between accuracy and conversion speed.