Research on the Method of Parity Checker Design Based on Evolvable Hardware

被引：0

作者：

Wang Kuifu ^{[1
]}

Yan Jingfeng ^{[1
]}

机构：

[1] Xuchang Univ, Sch Comp Sci & Technol, Xuchang 461000, Henan, Peoples R China

来源：

2010 THE 3RD INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND INDUSTRIAL APPLICATION (PACIIA2010), VOL III | 2010年

关键词：

evolvable hardware; genetic algorithm; parity checker;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Evolvable hardware design is a new research focus. This paper proposes the method of parity checker design based on evolvable hardware through an introduction to the fundamentals of evolutionary circuit design. The features of algorithm used in this paper are as follows: evolutionary algorithm is combined with multi-objective optimization algorithm, and an optimized logic circuit is evolved and designed with little computing load and high efficiency according to the multiple objectives of design. The simulation results of parity checker's functions indicate that the algorithm used in this paper is better than the method of traditional circuit design in terms of both gate circuit resources and search time.

引用

页码：57 / 59

页数：3