Evaluation of CORDIC algorithms for FPGA design

被引：64

作者：

Valls, J ^{[1
]}

Kuhlmann, M

Parhi, KK

机构：

[1] Univ Politecn Valencia, Dept Ingn Elect, Valencia 46730, Spain

[2] Broadcom Corp, Irvine, CA 92619 USA

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2002年 / 32卷 / 03期

关键词：

CORDIC; FPGA; Two's complement; redundant arithmetic;

D O I：

10.1023/A:1020205217934

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.

引用

页码：207 / 222

页数：16

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