Coping with latency in SOC design

被引：72

作者：

Carloni, LP ^{[1
]}

Sangiovanni-Vincentelli, AL ^{[1
]}

机构：

[1] Univ Calif Berkeley, Berkeley, CA 94720 USA

来源：

IEEE MICRO | 2002年 / 22卷 / 05期

关键词：

D O I：

10.1109/MM.2002.1044297

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Latency-insensitive design is the foundation of a correct-by-construction methodology for soc design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.

引用

页码：24 / 35

页数：12

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