Low-Power 3D Integration using Inductive Coupling Links for Neurotechnology Applications

被引:0
作者
Fletcher, Benjamin J. [1 ]
Das, Shidhartha [2 ]
Poon, Chi-Sang [3 ]
Mak, Terrence [1 ]
机构
[1] Univ Southampton, Dept Elect & Comp Sci, Southampton, Hants, England
[2] ARM Ltd, Cambridge, England
[3] MIT, Harvard MIT Hlth Sci & Technol, Cambridge, MA 02139 USA
来源
PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | 2018年
关键词
SILICON; DESIGN;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Three dimensional system integration offers the ability to stack multiple dies, fabricated in disparate technologies, within a single IC. For this reason, it is gaining popularity for use in sensor devices which perform concurrent analogue and digital processing, as both analogue and digital dies can be coupled together. One such class of devices are closed-loop neuromodulators; neurostimulators which perform real-time digital signal processing (DSP) to deliver bespoke treatment. Due to their implantable nature, these devices are inherently governed by very strict volume constraints, power budgets, and must operate with high reliability. To address these challenges, this paper presents a low-power inductive coupling link ([CL) transceiver for 3D integration of digital CMOS and analogue BiCMOS dies for use in closed-loop neuromodulators. The use of an ICL, as opposed to through silicon vias (TSVs), ensures high reliability and fabrication yield in addition to circumventing the use of voltage level conversion between disparate dies, improving power efficienQc The proposed transceiver is experimentally evaluated using SPICE as well as nine traditional TSV baseline solutions. Results demonstrate that, whilst the achievable bandwidth of the TSV-based approaches is much higher, for the typical data rates demanded by neuromodulator applications (0.5- 1 6bps) the ICI, design consumes on average 36.7% less power through avoiding the use of voltage level shifters.
引用
收藏
页码:1211 / 1216
页数:6
相关论文
共 18 条
  • [1] Al-Dujaily R., 2011, 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI), P318, DOI 10.1109/SAMOS.2011.6045478
  • [2] Demystifying 3D ICs: The procs and cons of going vertical
    Davis, WR
    Wilson, J
    Mick, S
    Xu, M
    Hua, H
    Mineo, C
    Sule, AM
    Steer, M
    Franzon, PD
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06): : 498 - 510
  • [3] Ditzel D., 2014, IEEE HOT CHIPS 26 S
  • [4] Greenwald E, 2016, MED BIOL ENG COMPUT, V54, P1, DOI 10.1007/s11517-015-1429-x
  • [5] High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
    Kim, Joohee
    Pak, Jun So
    Cho, Jonghyun
    Song, Eakhwan
    Cho, Jeonghyeon
    Kim, Heegon
    Song, Taigon
    Lee, Junho
    Lee, Hyungdong
    Park, Kunwoo
    Yang, Seungtaek
    Suh, Min-Suk
    Byun, Kwang-Yoo
    Kim, Joungho
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (02): : 181 - 195
  • [6] Kuroda T, 2014, INT EL DEVICES MEET
  • [7] Lim S.K., 2012, Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
  • [8] Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect
    Miura, N
    Mizoguchi, D
    Sakurai, T
    Kuroda, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) : 829 - 837
  • [9] Simple accurate expressions for planar spiral inductances
    Mohan, SS
    Hershenson, MD
    Boyd, SP
    Lee, TH
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (10) : 1419 - 1424
  • [10] Mojarradi M., 2003, WO Patent App, Patent No. [PCT/ US2002/ 037,419, 2002037419]