A Versatile Readout System for Small to Medium Scale Gaseous and Silicon Detectors

被引:23
|
作者
Calvet, Denis [1 ]
机构
[1] CEA Saclay, Inst Rech Lois Fondamentales Univers, F-91191 Gif Sur Yvette, France
基金
欧洲研究理事会;
关键词
Detector front-end electronics; FPGAs; network based data acquisition systems; TIME PROJECTION CHAMBERS;
D O I
10.1109/TNS.2014.2299312
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design and performance of a readout system for gaseous and silicon detectors built for the Minos nuclear physics experiment. A major constraint was to provide a multi-thousand channel, high performance readout system with low manpower effort and tight cost. This was achieved by the re-use of some earlier ASIC and front-end card (FEC) developments, the design of a new digital readout card, called the Feminos, and the use of commercial off-the-shelf components. The proposed system fully exploits the capability of the existing 72-channel AFTER chip designed for the T2K experiment and allows seamless migration to the 64-channel AGET chip, a pin-compatible evolution under production by the GET collaboration. The Feminos is a low complexity card designed to read out a FEC equipped with four AFTER chips (T2K model) or a newly assembled FEC populated with four AGET chips. The trigger clock module (TCM) is a synchronization board that allows system scaling up to 6912 channels with 24 Feminos and FECs, a commercial Gigabit Ethernet switch, and a data acquisition PC. The design of the Feminos hardware, firmware and embedded software are detailed and it is explained how high performance, rapid development and low cost were reached. System operation and data acquisition throughput scaling with multiple Feminos are investigated.
引用
收藏
页码:675 / 682
页数:8
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