The grand challenges of plasma etching: a manufacturing perspective

Plasma etching has been enabling nano-electronic fabrication since the 1980s; during this time, transistor size has shrunk by nearly two orders of magnitude, starting at 1.0 mu m in the mid 80s to similar to 0.01 mu m today. The manufacturing of these devices requires overcoming a series of challenges, ranging from continuous innovation on device integration to extend Moore's law to breaking tradeoffs on the perennial challenge of aspect ratio-dependent etching. In this paper, we will review four key areas in etch manufacturing: uniformity, defects, surface precision and 'sticky'/non-volatile etch materials. In the uniformity section, we will discuss the challenges for microscopic uniformity, such as localized feature dimension variations; macroscopic uniformity, such as performance at the extreme edge of the wafer; and repeatable uniformity, meaning wafer-to-wafer, lot-to-lot and chamber-to-chamber performance. While defect management is successful with in situ plasma cleans, one must be cognizant of the choice of clean chemistry. In surface precision, we look at the approach of atomic layer etching and how it can be successful in a manufacturing environment. Finally, in the non-volatile material section, we review technology drivers for DRAM (dynamic random access memory) and NAND flash memory in the microelectronics Si industry, with focus on the utilization of such materials and what it means to etch equipment manufacturers.