Executing Java']Java programs with transactional memory

被引：8

作者：

Carlstrom, Brian D. ^{[1
]}

Chung, JaeWoong ^{[1
]}

Chafi, Hassan ^{[1
]}

McDonald, Austen ^{[1
]}

Minh, Chi Cao ^{[1
]}

Hammond, Lance ^{[1
]}

Kozyrakis, Christos ^{[1
]}

Olukotun, Kunle ^{[1
]}

机构：

[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA

来源：

SCIENCE OF COMPUTER PROGRAMMING | 2006年 / 63卷 / 02期

基金：

美国国家科学基金会;

关键词：

transactions; feedback optimization; multiprocessor architecture;

D O I：

10.1016/j.scico.2006.05.006

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Parallel programming is difficult due to the complexity of dealing with conventional lock-based synchronization. To simplify parallel programming, there have been a number of proposals to support transactions directly in hardware and eliminate locks completely. Although hardware support for transactions has the potential to completely change the way parallel programs are written, initially transactions will be used to execute existing parallel programs. In this paper we investigate the implications of using transactions to execute existing parallel Java programs. Our results show that transactions can be used to support all aspects of Java multithreaded programs, and once Java virtual machine issues have been addressed, the conversion of a lock-based application into transactions is largely straightforward. The performance that these converted applications achieve is equal to or sometimes better than the original lock-based implementation. (c) 2006 Elsevier B.V. All rights reserved.

引用

页码：111 / 129

页数：19

共 48 条

[11]

CARLSTROM BD, 2006, PLDI 06 P 2006 ACM S

[12] The Jrpm system for dynamically parallelizing Java']Java programs [J].

Chen, MK ;

Olukotun, K .

30TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2003, :434-445

[13]

FLANAGAN C, 2005, WORKSH T SYSTEMS

[14] Tradeoffs in buffering memory state for thread-level speculation in multiprocessors [J].

Garzarán, MJ ;

Prvulovic, M ;

Llaberiá, JM ;

Viñals, V ;

Rauchwerger, L ;

Torrellas, J .

NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2003, :191-202

[15]

Hammond L, 2004, CONF PROC INT SYMP C, P102

[16] The Stanford Hydra CMP [J].

Hammond, L ;

Hubbert, BA ;

Siu, M ;

Prabhu, MK ;

Chen, M ;

Olukotun, K .

IEEE MICRO, 2000, 20 (02) :71-84

[17]

HAMMOND L, 2004, ASPLOS 11, P1

[18]

HARRIS T, 2003, OOPSLA 03, P388, DOI DOI 10.1145/949305.949340

[19]

Harris Tim., 2005, PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, P48, DOI DOI 10.1145/1065944.1065952

[20]

Herlihy M., 2003, P 22 ANN S PRINC DIS, P92, DOI DOI 10.1145/872035.872048

← 1 2 3 4 5 →