System Aware DUT Design for Optimum On-Wafer Noise Measurement

被引：0

作者：

Chen, Chih-Hung ^{[1
]}

Yang, Benson ^{[1
,2
]}

Chu, Pei-Hsien ^{[1
]}

Brown, Graham ^{[1
]}

Das, Saswati ^{[1
]}

机构：

[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON, Canada

[2] Sunnybrook Res Inst, Phys Sci Platform, Toronto, ON, Canada

来源：

PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) | 2018年

关键词：

device-under-test design; thermal noise; high-frequency noise characterization; on-wafer noise measurement; HIGH-FREQUENCY NOISE; MOSFETS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a system-aware design of device-under-tests (DUT) for optimum high-frequency (HF) on-wafer noise measurement. It overcomes the challenges in modeling the bias and geometry dependence of noise sources due to the voltage drop in the interconnections at the output port of a large DUT. It also prevents the measurement inaccuracy resulted from insufficient noise from a small DUT. Experimental data and suggested device sizes for different technologies are presented.

引用

页码：206 / 209

页数：4

共 14 条

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