Architecture of low-power embedded ROMs

In ASICs, memories take an important part from the power consumption point of view. Large and low-power embedded memories are today required in many designs. This paper describes a new ROM compiler dedicated to low-power embedded applications. Several circuit techniques for reducing the power consumption such as the multi-block architecture, selective precharge, pipe-line de coding, auto-timing structure have been used. The design methodology and the user interface of the compiler are presented. Achieved results are satisfactory compared to those obtained with a former compiler.