A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node

被引：7

作者：

Hu, Yu-Chen ^{[1
]}

Lin, Chun-Pin ^{[2
]}

Chang, Yao-Jen ^{[1
]}

Chang, Nien-Shyang ^{[2
]}

Sheu, Ming-Hwa ^{[2
]}

Chen, Chi-Shi ^{[2
]}

Chen, Kuan-Neng ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, Taiwan

[2] Natl Appl Res Labs, Chip Implementat Ctr, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2015年 / 62卷 / 12期

关键词：

3-D integration; heterogeneous;

D O I：

10.1109/TED.2015.2487041

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.

引用

页码：4343 / 4348

页数：6

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