The past, present and future of high-k/metal gates

被引:23
作者
Choi, Kisik [1 ]
Ando, Takashi [2 ]
Cartier, Eduard [2 ]
Kerber, Andreas [1 ]
Paruchuri, Vamsi [3 ]
Iacoponi, John [1 ]
Narayanan, Vijay [2 ]
机构
[1] IBM Albany NanoTech Ctr, GLOBALFOUNDRIES, Albany, NY 12203 USA
[2] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
[3] IBM Albany NanoTech Ctr, Albany, NY 12203 USA
来源
SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 3 | 2013年 / 53卷 / 03期
关键词
INTERFACE;
D O I
10.1149/05303.0017ecst
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
Like other technology components of the semiconductor industry, the high-k/metal gate has also continued innovation since its introduction to the 45 nm node. In order to fulfill the ever-increasing power/performance requirements for the future devices, new device architectures are being introduced and the high-k/metal gate should evolve in accordance. In this paper, the development history of the high-k/metal gate stack will be reviewed and the qualities required for the high-k/metal gate stack to match with the future devices will be discussed.
引用
收藏
页码:17 / 26
页数:10
相关论文
共 35 条
[1]  
Ando T., 2011, SISC 2011
[2]  
[Anonymous], VLSI S
[3]  
[Anonymous], IEDM
[4]  
[Anonymous], [No title captured]
[5]  
Auth C., 2012, 2012 IEEE Symposium on VLSI Technology, P131, DOI 10.1109/VLSIT.2012.6242496
[6]  
Bersuker G., 2010, IEEE TED, V57
[7]  
Bohr M., 2011, INT ELECT DEVICES M, p1.1.1, DOI DOI 10.1109/IEDM.2011.6131469
[8]   Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization Of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies [J].
Cartier, E. ;
Kerber, A. ;
Krishnan, S. ;
Linder, B. ;
Ando, T. ;
Frank, M. M. ;
Choi, K. ;
Narayanan, V. .
PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 9, 2011, 41 (03) :337-348
[9]  
Cartier E, 2009, 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P42
[10]  
Choi K., 2009, VLSI S, P138